1. Field of the Invention
This invention relates to Wireless Baseband Processors and Forward Error-Correction (FEC) Codes for 3rd Generation (3G) Wireless Mobile Communications More particularly, the invention relates to a very high speed Turbo Codes Decoder using diversity processing and pipelined Max Log-MAP decoders for 3G Code Division Multiple Access (CDMA) 2000 and 3G Wideband Code Division Multiple Access (WCDMA).
2. Description of Prior Art
Diversity processing computes signals from two separate antennas using so-called xe2x80x9cmultipathxe2x80x9d signals that arrive at the terminal via different routes after being reflected from buildings, trees or hills. Diversity processing can increase the signal to noise ratio (SNR) more than 6 dB, which enables 3G systems to deliver data rates up to 2 Mbit/s.
Turbo Codes decoding is based upon the classic forward error correction concepts that include the use of recursive systematic constituent (RSC) Encoders and Interleayers to reduce Eb/N0 for power-limited wireless applications such as digital 3G Wireless Mobile Communications.
A Turbo Codes Decoder is an important baseband processor of the digital wireless communication Receiver, which was used to reconstruct the corrupted and noisy received data and to improve BER (10xe2x88x926) throughput. FIG. 1 shows an example of a diversity processing 3G Receiver with a Turbo Codes Decoder 13 which decodes data RXDa and RXDb from Demodulators 11 and Soft Decoders 12, and sends decoded data to the Media Access Control (MAC) layer 14. The data from the two received data paths pass through two diversity antennas, two Demodulators 11, and two Soft Decoders 12 to produce soft decoded data RXDa and RXDb for the Turbo Codes Decoder 13.
A widely used Forward Error Correction (FEC) scheme is the Viterbi Algorithm Decoder in both wired and wireless applications. A drawback of the Viterbi Algorithm Decoder is that it requires a long wait for decisions until the whole sequence has been received. A delay of six times the memory processing speed of the received data is required for decoding. One of the more effective FEC schemes, with higher complexity, uses a maximum a posteriori (MAP) algorithm to decode received messages. The MAP algorithm is computationally complex, requiring many multiplications and additions per bit to compute the posteriori probability. A major difficulty with the use of the MAP algorithm has been the implementation in semiconductor ASIC devices. The complexity of the multiplications and additions slow down the decoding process and reduce the throughput data rates. Furthermore, even under the best conditions, multiplication operations in the MAP algorithmrequires implementation using large circuits in the ASIC. The result is costly design and low performance in bit rates throughput.
Recently, the 3rd Generation Partnership Project (3GPP) organization introduced a new class of error correction codes using parallel concatenated codes (PCCC) that include the use of the classic recursive systematic constituent (RSC) Encoders and Interleavers as shown in FIG. 3. An example of the 3GPP Turbo Codes PCCC with 8-states and rate ⅓ is shown in FIG. 3. Data enters the two systematic encoders 3133 separated by an interleaver 32. An output codeword consists of the source data bit followed by the output bits of the two encoders.
Other prior work relating to error correction codes was performed by Berrou et al., describing parallel concatenated codes which are complex encoding structures that are not suitable for portable wireless device. Another patent U.S. Pat. No. 6,023,783 to Divsalar et al. describes an improved encoding method over Berrou et al., using mathematical concepts of parallel concatenated codes. However, patents by Berrou et al., Divsalar et al., and others only describe the concept of parallel concatenated codes using mathematical equations which are good for research in deep space communications and other government projects, but are not feasible, economical, and suitable for consumer portable wireless devices. In these prior systems, the encoding of data is simple and can be easily implemented with a few xor and flip-flop logic gates. But decoding the Turbo Codes is much more difficult to implement in ASIC or software. The prior art describes briefly the implementation of the Turbo Codes Decoder which are mostly for deep space communications and requires much more hardware, power consumption and costs.
Another prior art example of a 16-state Superorthogonal Turbo Codes (SOTC) is shown in FIG. 2. It is identical to the previous 3GPP Turbo Codes PCCC except a Walsh Code Generator substitutes for the XOR binary adder. Data enters the two systematic encoders 21, 23 separated by an interleaver 22. An output codeword consists of the two Walsh Codes output from the two encoders.
All the prior art Turbo Codes fail to provide simple and suitable methods and architectures for a Turbo Codes Decoder as it is required and desired for 3G cellular phones and 3G personal communication devices, including the features of high speed data throughput, low power consumption, lower costs, limited bandwidth, and limited power transmitter in noisy environments.
The present invention is directed to Turbo Code Decoders using diversity processing to implement a more efficient, practical and suitable architecture and method to achieve the requirements for 3G wireless systems, including the features of higher speed data throughput, lower power consumptions, lower costs, and suitable for implementation in ASIC or DSP codes. The present invention encompasses several improved and simplified Turbo Codes Decoder methods and devices to deliver higher speed and lower power consumption, especially for 3G applications. Diversity processing can increase the signal to noise ratio (SNR) more than 6 dB, which enables 3G systems to deliver data rates up to 2 Mbit/s. As shown in FIG. 4, an exemplary embodiment of the Turbo Codes Decoder utilizes two parallel Turbo Codes Decoders for diversity processing. Each Turbo Codes Decoder has serially concatenated Soft-input Soft-output logarithm maximum a posteriori (SISO Log-MAP) Decoders. The two decoders function in a pipelined scheme with delay latency N. While the first decoder is decoding data stored in the second-decoder-Memory, the second decoder performs decoding for data stored in the first-decoder-Memory, which produces a decoded output every clock cycle. As shown in FIG. 6, the Turbo Codes Decoder utilizes a Sliding Window of Block N on the input buffer memory to decode data per block N, which improves processing efficiency. Accordingly, several objects and advantages of the Turbo Codes Decoder are:
To implement diversity processing to increase the signal to noise ratio (SNR).
To deliver higher speed throughput and be suitable for implementation in application specific integrated circuit (ASIC) designs or digital signal processor (DSP) codes.
To utilize SISO Log-MAP decoders for faster decoding and simplified implementation in ASIC circuits and DSP codes with the use of binary adders for computation.
To perform re-iterative decoding of data back-and-forth between the two Log-MAP decoders in a pipelined scheme until a decision is made. In such pipelined scheme, decoded output data is produced each clock cycle.
To utilize a Sliding Window of Block N on the input buffer memory to decode data per block N for improved pipeline processing efficiency
To provide higher performance in term of symbol error probability and low BER (10xe2x88x926) for 3G applications such as 3G W-CDMA, and 3G CDMA2000 operating at very high bit-rate up to 100 Mbps, in a low power, noisy environment.
To utilize a simplified and improved SISO Log-MAP decoder architecture, including a branch-metric (BM) calculations module, a recursive state-metric (SM) forward/backward calculations module, an Add-Compare-Select (ACS) circuit, a Log-MAP posteriori probability calculations module, and an output decision module.
To reduce complexity of multiplier circuits in MAP algorithm by performing the entire MAP algorithm in Log Max approximation using binary adder circuits, which are more suitable for ASIC and DSP codes implementation, while still maintaining a high level of performance output.
To design an improve Log-MAP Decoder using high level design language (HDL) such as Verilog, system-C and VHDL, which can be synthesized into custom ASIC and Field Programmable Gate Array (FPGA) devices.
To implement an improve Log-MAP Decoder in DSP (digital signal processor) using optimized high level language C, C++, or assembly language.
Still further objects and advantages will become apparent to one skill in the art from a consideration of the ensuing descriptions and accompanying drawings.